As a solid-state imaging device which is mounted on a digital still camera, or a digital video camera, a CMOS image sensor (hereinafter, abbreviated to CIS) has been known. In addition, the CIS is used in an imaging apparatus for sensing, and in a case of such a use, rapidity of operations is particularly necessary.
For acceleration of operations of the CIS, a method in which an AD conversion unit (hereinafter, abbreviated to ADC) is provided to one, or a relatively small number of pixels, and a plurality of the ADCs are operated in parallel has been known.
In such a method, optical characteristics of pixels are sacrificed when providing the ADC in the same substrate of the pixel.
Therefore, a configuration in which pixels and ADCs are provided on separate substrates, and both the substrates are connected by being bonded using Cu—Cu bonding in order not to sacrifice optical characteristics of the pixels has been proposed. In addition, since a size of one ADC usually corresponds to a size of a plurality of pixels, the plurality of pixels on the separate substrate are correspondingly connected to the one ADC (for example, refer to PTL 1).
FIG. 1 is a conceptual diagram of a CIS in which pixels and ADCs are provided on different substrates. That is, the CIS 10 is configured by an upper substrate 11 and a lower substrate 12, and the upper substrate 11 and the lower substrate 12 are bonded using Cu—Cu bonding, or the like, and are connected to each other at corresponding portions.
FIGS. 2A and 2B schematically illustrate respective circuit configurations of the upper substrate 11 and the lower substrate 12 of the CIS 10.
As illustrated in FIG. 2A, a plurality of pixels 21 which are arranged in a matrix, a vertical scanning unit 23, and a horizontal scanning unit 24 are provided on the upper substrate 11. Each of the plurality of pixels 21 is divided into one pixel block 22 by 4*4 pixels according to an ADC 31 which will be described later. The pixel 21 generates a charge corresponding to input light using photoelectric conversion processing, accumulates the charge, and transmits a pixel signal corresponding to the accumulated charge to the ADC 31 of the lower substrate 12 at a scanning timing based on a control from the vertical scanning unit 23 and the horizontal scanning unit 24.
As illustrated in FIG. 2B, the lower substrate 12 is provided with the plurality of ADCs 31 which respectively correspond to the pixel block 22 of the upper substrate 11, a digital signal processing unit 32, a timing generation unit 33, and a DAC 34. Each ADC 31 converts analog pixel signals which are sequentially transmitted from the plurality of pixels 21 which belong to corresponding pixel block 22 into a digital signal.
For example, a pixel block 22 on the upper left of the upper substrate 11 corresponds to an ADC 31a on the upper left of the lower substrate 12. In addition, similarly, a pixel block 22 on the upper right of the upper substrate 11 corresponds to an ADC 31e on the upper right of the lower substrate 12. That is, respective occupying areas and shapes thereof of a pixel block 22 on the upper substrate 11 and an ADC 31 on the lower substrate 12 are set so as to match with each other.
FIG. 3 illustrates a configuration example of the ADC 31. The ADC 31 includes a comparison unit 41 and a latch unit 42. The comparison unit 41 compares analog pixel signals which are sequentially transmitted from each pixel 21 of a corresponding pixel block 22 with a Ramp signal which is input from the DAC 34, and outputs a comparison result thereof to the latch unit 42. The latch unit 42 maintains an input code value when a Ramp signal crosses the pixel signal based on the comparison result of the comparison unit 41. The code value which is maintained in the latch unit 42 is read out in the digital signal processing unit 32 as a digital pixel signal.
FIG. 4 illustrates general scanning order of 4*4 pixels which configure a pixel block 22. In the figure, a rectangle of a thin line denotes a pixel 21, a thick line denotes a pixel block 22 which is correlated with one ADC 31, numbers denote positions of pixels, and arrows denote scanning order of pixels. In addition, a pixel located on an X row and a Y column is also described as a pixel (X,Y).
For example, in a pixel block of which a pixel (0,0) is on the upper left top, scanning is started in the right horizontal direction by setting a pixel on the upper left (0,0) as the starting point, and a row to be scanned is moved in the lower vertical direction sequentially, and the lower right pixel (0,3) is lastly read out. Similarly, in another pixel block 22, as well, scanning is started in the right horizontal direction by setting a pixel 21 on the upper left, a row to be scanned is sequentially moved in the lower vertical direction, and a pixel 21 on the lower right is lastly read out.
FIG. 5 illustrates a configuration example of each pixel 21 for changing scanning order in a pixel block 22 to the horizontal direction and the vertical direction, as illustrated in FIG. 4.
A pixel 21 is configured by a photodiode (PD) 51, a transfer gate (Trf) 52, a floating diffusion (FD) 53, an amplification transistor (Amp) 54, a selection transistor for vertical scanning (Sel) 55, a selection transistor for horizontal scanning (Sel) 56, a reset transistor (Rst) 57, power source wiring 58, and a signal line 59.
In the pixel 21, a charge which is generated in the PD 51 as a photoelectric conversion device is transmitted to the FD 53 which is connected to a gate of the Amp 54 through the Trf 52. At this time, when the Sel 55 which is controlled by the vertical scanning unit 23, and the Sel 56 which is controlled by the horizontal scanning unit 24 are turned on, the Amp 54 outputs a voltage signal corresponding to a potential of the charge which is maintained in the FD 53 to an ADC 31 in the rear stage through the vertical signal line 59. In addition, the charge which is accumulated in the FD 53 is thrown away in the power source wiring 58 when the Rst 57 is turned on.